| 摘要 |
PURPOSE:To manufacture an MESFET having gate length of the submicron order with favolrable controllability of yield by a method wherein after ion implantation is performed through a window hole to a first semiconductor layer to form partially a high resistance layer, etching is performed to form a groove of width at the base narrower than width of the window hole, and then a gate metal is evaporated. CONSTITUTION:An N type GaAs active layer 2 and an N<+> type GaAlxAs1-x layer 7 are formed on a semiinsulating GaAs substrate 1 using the opitaxial method or using together with the ion implantation method. Then an insulating film 8 is formed, and a hole is opened using a photoresist 5. Then, an AuGe metal is evaporated, a source electrode 3 and a drain electrode 4 are formed using the usual lift-off method, and sintering is performed at a proper temperature to obtain ohmic contact. Then, a hole of width W1 is opened using the photo resist 5. Then, ion implantation is performed from the open hole part to convert partially the N<+> type GaAlxAs1-x layer 7 into a high resistance layer 9. Then, only the high resistance GaAlxAs1-x layer 9 is etched selectively from the open hole part. |
