| 摘要 |
PURPOSE:To reduce the effect to the system clock cycle owing to an increase of memories by using a means which selects and delivers the duplicate access requests to plural operation state checking circuits and memories. CONSTITUTION:Operation state checking circuits 220, 221, etc. supply access requests CPU0 and CPU1 via memory means 210 and 211. These requests are collated with operation state registers 250, 252, etc. Then an access request is delivered if the actuation is possible. A duplication preventing circuits 300 uses the plural access requests given from means 210 and 211 as inputs to select either one of both access requests in response to the prescribed priority order in case the memories designated by said inputs are coincident and duplicated with each other. In such a way, the effect to the system clock cycle due to an increase of memories can be reduced with use of operation state checking circuits and duplication a preventing circuit. |
