SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME

摘要

1,263,617. Semi-conductor devices. SONY CORP. 23 May, 1969 [25 May, 1968], No. 26433/69. Heading H1K. A semi-conductor device such as the NPN Si transistor Trn shown includes a P(N) type substrate 101 having diffused therein an N(P) type region 103A and a layer 106 vapour deposited thereon. The layer 106 includes an annular N+(P+) type polycrystalline region 106A formed over part of the region 103A and surrounding a monocrystalline N(P) type region 103A1, and N+(P+) type regions 136A also form in the monocrystalline material both inside and outside the annulus of the polycrystalline region 106A. The polycrystalline material forms because of pre-treatment of selected areas of the surface of the substrate 101 prior to vapour deposition of the layer 106. This pretreatment may consist of roughening or scratching or deposition of Si or SiO 2 . The layer 106 is basically almost intrinsic, but redistribution of impurities from the surface of the substrate 101 either during or after deposition imparts the desired conductivity properties to the layer 106. Such redistribution occurs far more rapidly in the polycrystalline material than in the monocrystalline material, with the result that the polycrystalline material and the monocrystalline regions in its immediate vicinity become more highly conductive than the bulk of the monocrystalline material. As shown a collector electrode 113AC is applied to the region 106A and base and emitter electrodes are applied to diffused base and emitter regions 108A, 109A in the central N type collector region 103A1. Further high conductivity regions 136A may also be diffused adjacent the polycrystalline material 106A simultaneously with formation of the emitter region 109A. The structure illustrated also includes a PNP transistor Trp formed similarly to the transistor Trn, but having an N+ type isolation zone 103B separating it from the substrate 101. A high conductivity N+ type polycrystalline annular region 106B is also formed in the layer 106 above part of'the isolation zone 103B. Further P+ type polycrystalline isolation regions 106C are also provided between the two transistors. The electrodes in the embodiments are of Al.