| 摘要 |
PURPOSE:To synchronize the output of a frequency divider with a bit synchronizing clock for a long time by reducing the attenuation of a control voltage ap- plied to a VCO as less as possible if an input signal to a transmission interface circuit is disappeared. CONSTITUTION:A signal disconvection detection circuit 10 detects that an input signal to the transmission interface circuit 1 is missing. When times of two timers in the detection circuit 10 are assumed as t1, t2 and also the relation of t2>t1 exists, the passing of the signal in a gate circuit 11 is blocked during t1< t<t2 and the input of a charge pump circuit 6 is opened. Thus, a normal signal is inputted to a phase comparator 5 from a level converting circuit 4 by a Q of a tank circuit 2 for the time t1 after the signal input to the detection circuit 10 is missing and a normal control voltage is fed to the VCO8 from a low pass filter (LPF)7. After the time t1, the gate circuit 11 blocks the output, the output of the LPF7 is decreased gradually and the output of a frequency divider 9 goes to a signal in synchronizing with the bit synchronizing clock. |
