发明名称 DATA MEMORY
摘要 PURPOSE:To read at a high speed the reduced data obtained from sampling and the revolved data in suppressing the increase of control circuits, by dividing the data circulation shifts within a block into the unit circulation shifts and the bit circulation shifts. CONSTITUTION:The data shift at the time of write mode is performed by a unit shift circuit 3 of the input side and a bit shift circuit 4 of the input side. For the unit shift of the input side, latches 31-34 supply 8 bit of input data in common with the latch of 8 bits and 4-phase clocks are defined to LOAD1-4 to obtain the data shifted in the right circulation every unit at latches 31-34. This unit shifted 32-bit data is supplied to the circuit 4 and then to 8-bit circulation shift registers 41-44 every 8 bits. Then the data is shifted with circulation to the right by a prescribed amount in response to the sub-block position information and the bit position information fed from a line counter.
申请公布号 JPS6057446(A) 申请公布日期 1985.04.03
申请号 JP19830165501 申请日期 1983.09.08
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SASANUMA HIROSHI;NISHINO YASUKAZU
分类号 G06F12/00;G06F12/06;G06T3/00 主分类号 G06F12/00
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