发明名称 |
Semiconductor memory device |
摘要 |
A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of said row decoders for controlling the conduction state of the switching MOS transistors.
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申请公布号 |
US4509148(A) |
申请公布日期 |
1985.04.02 |
申请号 |
US19830493605 |
申请日期 |
1983.05.11 |
申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
ASANO, MASAMICHI;IWAHASHI, HIROSHI |
分类号 |
G11C8/10;G11C11/4076;G11C11/408;G11C17/12;(IPC1-7):G11C11/40 |
主分类号 |
G11C8/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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