发明名称 |
MOS Analog switch driven by complementary, minimally skewed clock signals |
摘要 |
An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.
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申请公布号 |
US4508983(A) |
申请公布日期 |
1985.04.02 |
申请号 |
US19830465408 |
申请日期 |
1983.02.10 |
申请人 |
MOTOROLA, INC. |
发明人 |
ALLGOOD, ROBERT N.;PETERSON, JOE W.;WHATLEY, ROGER A. |
分类号 |
H03K17/06;H03K17/16;(IPC1-7):H03K17/16;H03K17/687;H03K19/096 |
主分类号 |
H03K17/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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