| 摘要 |
<p>PURPOSE:To reduce the necessary multiplication number and the input addition number by giving the process to the real part of the complex input and the imaginary part via the real and imaginary signal processors each and then giving the addition and subtraction to both output through the post-process circuit with only the addition and subtraction to obtain the addition/subtraction output. CONSTITUTION:Real signal processor 16 carries out the basic conversion of RadixN including the phase offset which supplies each real part Xk<r> of N units of complex input signal and then delivers only the real part. In addition such processor 16, imaginary signal processor 17 is provided to carry out the basic conversion of RadixN containing the phase offset which supplies each imaginary part Xk<i> of the complex input signal and then delivers only the imaginary part. Then the outputs of processors 16 and 17 are applied to adder/subtractor circuit 19, and the NO.n output of processor 16 is defined as the imaginary part of NO.N-n. Then the No.n output of processor 17 is made to correspond to the real part of No.N-n. The addition and subtraction is given to each real and imaginary parts to give the operation to the output from No.0 to No.N, thus decreasing the necessary multiplication and input addition numbers each.</p> |
