Majority circuit - uses small number of memories and gates supplied with parity check bits divided into sets

摘要

Majority circuit constituted by a small number of standard commercial parts uses parity check bits divided into sets supplied to memories and gates. The circuit has two identical ROMs which each have eight addressed and data storage locations and whose outputs are supplied in various combinations to selected gates in a set of fifteen NAND gates. The outputs of all these NAND gates are supplied to an ORgate connected to an output terminal. The circuit input includes parity check bits which are divided into a set of eight bits supplied to one ROM, and a second set of eight bits that are supplied to the second ROM. A third set of single bits is supplied to selected NAND gates.