发明名称 JOSEPHSON JUNCTION MEMORY CHIP
摘要 PURPOSE:To increase the chip memory capacity without using many Josephson junction gates within a chip by circulating the information of large capacity to a super conduction loop connecting a transmission line, a writing gate of Josephson junction, an earth source and a sense gate control line. CONSTITUTION:If a remote terminal 35 of a transmission line 31 is short-circuited to an earth source 33, the current pulse trains have the same polarity with no attenuation and are totally reflected. Thus the delay time is equal to about double as much as the delay time between the near remote terminals of the line 31 when viewed from a near terminal 34. When a writing current pulse train Iw is supplied from a generation source 32, a writing gate 12 of Josephson junction is immediately switched to a voltage state from a superconduction state in case a control current Iy is impressed to a control line 15. Then the train Iw is switched to the side of the line 31 and then reflected by the source 33 via a sense gate control line 13 at the terminal 35. The train Iw is sent back to the terminal 34. The drive of the Iw is stopped immediately before the terminal 34, and at the same time the impression of the current Iy is cut off. Then the gate 12 is reset to the superconduction state from the voltage state. Thus the Iw passes again through the gate 12 and is totally reflected by the source 33.
申请公布号 JPS6055597(A) 申请公布日期 1985.03.30
申请号 JP19830162744 申请日期 1983.09.05
申请人 NIPPON DENKI KK 发明人 TAKAHASHI TSUNESUKE
分类号 G11C11/44;H01L39/22 主分类号 G11C11/44
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