| 摘要 |
PURPOSE:To obtain a memory of a nibble mode which has a normal actuation even with a single clock by validating just one of control signals sent successively and permiting the writing of just a data to a small area in case the cycle for successive transmission of data is larger than the cycle for successive transmission of control signals. CONSTITUTION:When the 1st memory start signal MGO which is sent to a terminal 13 from a CPU (not shown in the figure) is set at ''1'', ''1'' is delivered successively from DFF1-9 every time a single clock advances by a clock. While the 2nd memory start signal SMGO is delivered from a terminal 16 so that ''1'' is set only at T0-T1. A counter 37 is reset with the signal MGO and adds +1 to its value with reception of the signal SMGO. A selector 38 selects WE0, WE1, WE2 and WE3 when the value of the counter 37 is set at ''1'', ''2'', ''3'' and ''4'' respectively. |
