发明名称 COMPUTER
摘要 PURPOSE:To eliminate special hardware and reduce the scale of a device, and improve the reliability by composing one arithmetic control unit of two function- decentralized processors, and combining plural units into an (n)-tuple system. CONSTITUTION:Arithmetic control units 1a-1c each consist of two function- decentralized processors, i.e. a control processor and a diagnostic processor. When a start command is supplied to an optical arithmetic control unit, the arithmetic control unis 1a-1c informs a rise command by software through transmission lines 3 and 4 and also collate and synchronize data. A majority decision logical circuit 2 receives the input signals from the arithmetic control units 1a-1c to generate an output based upon majority decision logic, which is supplied to an external equipment through a control output line 7 and also fed back to the arithmetic control units 1a-1c through a control output monitor line 8.
申请公布号 JPS6055447(A) 申请公布日期 1985.03.30
申请号 JP19830163658 申请日期 1983.09.06
申请人 TOSHIBA KK 发明人 KURII HAJIME
分类号 G06F11/18 主分类号 G06F11/18
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