| 摘要 |
PURPOSE:To attain the record and reproduction with the same hardware even in case the media different in level of recording density are used, by compressing a bit and therefore having a margin of processing time. CONSTITUTION:An input signal is converted into the binary data after A/D conversion and supplied to an arithmetic logical circuit 7. In the 1st clock mode, the binary data is stored to a register 8 by inhibiting an operation of the circuit 7 via a logic control circuit 10, an order control circuit 11 and a control memory circuit 12. In the next clock mode, the compressed comparison data is read out of a coefficient memory circuit 6 in case the decision output obtained by a switch 9 is positive. Then the bit obtained in response to the comparison arithmetic result of the circuit 7 is set by the circuits 7 and 10, the memory 12 and the circuit 11 to obtain the compression data. No compression is carried out when the decision output of the switch 9 is negative. The result of the compression data is added with an error correction code or interleaved by a data memory 13 to be modulated and recorded. |
