发明名称 DATA RETRANSMISSION SYSTEM IN DATA TRANSFER DEVICE
摘要 PURPOSE:To improve the processing capability of a high-order control section by providing a confirming response detecting circuit, buffer control circuit, timer circuit and a direct memory access circuit to a data transfer device to process automatically the retransmission processing having been conducted by the high- order control section. CONSTITUTION:The buffer control circuit 40 managing a memory circuit 20 storing a transfer data, direct memory access circuit 30 started by the buffer circuit, timer circuit 50 and a confirming response detecting circuit detecting the conforming response of the data transmitted already from a received data are provided. When the high-order control section 70 writes a transfer data to the memory circuit 20 and requests transfer to the buffer control circuit 40, the buffer control circuit 40 starts the timer circuit 50 and the direct memory access circuit 30 and performs transfer. When a confirming response detection circuit 60 detects a negative response and can not detect the confirming response for a prescribed time, the direct memory access circuit 30 retransmits automatically the data already transmitted.
申请公布号 JPS6053348(A) 申请公布日期 1985.03.27
申请号 JP19830161565 申请日期 1983.09.02
申请人 NIPPON DENKI KK 发明人 YAMADA KENJI
分类号 H04L1/16;H04L1/18;(IPC1-7):H04L1/16 主分类号 H04L1/16
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