Static memory

摘要

In a MOS static RAM, data lines disposed in a memory array and common data lines to be coupled with the data lines through a data line selection circuit are supplied with bias voltages of a level lower than a power source voltage level through bias MOSFETs. Normally, where the stand-by period of the RAM is long, the bias voltages of the data lines and the common data lines are abnormally raised by the leakage currents or tailing currents of the bias MOSFETs. As a result, the data read-out speed of the RAM is lowered. Such abnormal potential increases of the data lines and the common data lines are prevented by connecting resistance elements of comparatively high resistances (such as made of polycrystalline silicon layers), between the respective data lines and common data lines and the ground point of the circuitry.