发明名称 |
Two's complement multiplier circuit |
摘要 |
A multiplication circuit includes a multiplying unit for multiplying a signed multiplier X represented in terms of the two's complement of n bits by a signed multiplicand Y represented in terms of two's complement of n bits to generate a signed multiplication output data of (2n-1) bits represented in terms of the two's complement, an exclusive-OR circuit for producing the exclusive-OR of the sign bits XS and YS of the respective values X and Y, and a selecting circuit for generating a sign bit "0" when the most significant bit of the multiplication output data from the multiplying unit is "0" and generating as a sign bit an output bit of the exclusive-OR circuit when the most significant bit is "1".
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申请公布号 |
US4507749(A) |
申请公布日期 |
1985.03.26 |
申请号 |
US19820423246 |
申请日期 |
1982.09.24 |
申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
OHHASHI, MASAHIDE |
分类号 |
G06F7/533;G06F7/508;G06F7/52;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/533 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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