发明名称 REDUCING SYSTEM OF PICTURE SIGNAL
摘要 PURPOSE:To reduce an original picture signal and eliminate slender lines in the direction of sub-scanning and reduce the original picture signal at high fidelity by providing plural picture signal line buffers, an exclusive OR gate and a selector etc. CONSTITUTION:Plural picture signal line buffers No.1-No.6 that inputs original picture signals (a) successively to a picture signal processing section of a facsimile device, and signals of EX-OR of buffers No.1, No.2 and No.4, No.5 are stored respectively in buffers No.3, No.6. Clock (b) synchronized with the signals (a) is added to input and output address counter 19A, 19B, and buffers No.1-No.6 are addressed. EX-OR gates 21A-21C, selectors 20A-20C, AND gates 22A, 22B etc. are provided for buffers No.1-No.6. Each bit is compared, and if there is change, bit of picture signal of erased 1 line is left, and when there is no change, bit of picture signal 1 line before or after the picture signal is left. Thus, the picture signal is reduced at high fidelity.
申请公布号 JPS6051069(A) 申请公布日期 1985.03.22
申请号 JP19830157163 申请日期 1983.08.30
申请人 TOSHIBA KK 发明人 KAGEYAMA KENICHI
分类号 H04N1/393;G06T3/40;H04N1/387 主分类号 H04N1/393
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