| 摘要 |
PURPOSE:To supply a timing signal which is not affected by a bit pattern of an input bipolar code and is stable, by executing the phase lock with a digital circuit to extract the timing signal. CONSTITUTION:A differentiator 11 generates a pulse designated by Fig. (c) at a rise point and a fall point of a signal 2a, and a digital bit synchronizing circuit 13 outputs a pulse signal 13a designated by Fig. (d) where the fall point of the output pulse is synchronized with the output of the differentiator 11. A frequency divider 14 divides the frequency of this signal 13a to output a signal 14a designated by Fig. (e). The first DFF15 is provided for delaying the signal 14a by a 1/4 period, and a timing signal designated by Fig. (f) is obtained in an output terminal Q. This timing signal (f) is applied to a clock input terminal T of the second DFF5 to obtain decoded received data indicated by Fig. (g) from a terminal 6. |
