发明名称 TEST FACILITATING CIRCUIT
摘要 PURPOSE:To contrive the reduction in the number of test controlling pins by a method wherein an LSI is provided with a test mode input pin and a mode switching circuit, so as to utilize a signal input pin also for the input of a test control signal by mode switching. CONSTITUTION:In the normal case, the test mode signal fed to the test mode signal input pin 2 is kept false, when the signals obtained via system signal input pins 5a and 5b are used as system input signals 6a and 8c as they are. At this time, there are no influences on the test control signals 8a and 8b in the presence of AND gates 7A and 7B, and the LSI performs the original action. Next, the signal 4a is turned true on the test mode, when the signals from the pins 5a and 5b can be directly changed into the signals 8a and 8b. During this test control, there are the cases where the input is preferable in being transmitted to the system or not preferable, however, in the latter case, it is kept gated by means of the AND gate 7c as the system input signal 8c.
申请公布号 JPS6050934(A) 申请公布日期 1985.03.22
申请号 JP19830157199 申请日期 1983.08.30
申请人 TOSHIBA KK 发明人 TSUBOUCHI TAKUMI
分类号 G11C29/00;G01R31/26;G01R31/28;G01R31/3185;G11C29/56;H01L21/66;H01L21/822;H01L27/04 主分类号 G11C29/00
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