发明名称 TIMING PULSE GENERATING CIRCUIT
摘要 PURPOSE:To set variably the leading edge and the trailing edge by generating a switching control pulse in accordance with a time delayed by a delaying circuit for correction, and also in accordance with the output of a coarse adjustment timing pulse generating circuit, and generating selective gate operation by its pulse. CONSTITUTION:The leading edge of output pulse of a coarse adjustment timing pulse generating circuit 1 is delayed by a time tON determined by a delaying circuit 10 and outputted. On the other hand, its trailing edge is delayed by a time tOFF determined by a delaying circuit 12 and outputted. Its time tON is determined by a delay time of output of the circuit 10 selected by the value set to a register 10b. Also, the time tOFF is determined by a delay time of the output of the circuit 12 selected by the value set to the register 12b. Therefore, the leading edge of the output timing pulse and also the trailing edge can be set variably.
申请公布号 JPS6051021(A) 申请公布日期 1985.03.22
申请号 JP19830158214 申请日期 1983.08.30
申请人 FUJITSU KK 发明人 FUJISAKI KAZUO;TATEISHI MAKOTO
分类号 H03K5/135;H03K5/13 主分类号 H03K5/135
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