发明名称 TIMER CONTROLLING CIRCUIT
摘要 <p>PURPOSE:To obtain a timer controlling circuit constituted of a small quantity of hardware by detecting and holding overflow or underflow from the result of operation of an updating circuit, direction of updating and a count command signal. CONSTITUTION:Counted value of each timer stored in a register file 1 is operated by an adder-subtracter 5 basing on addition and subtraction constant and direction of updating stored in a register file 2 and command of count command signal of each timer held in FF group 4, and stored again in the register file 1. At this time, output of the adder-subtracter 5, that is, overflow or underflow of the result of operation is detected by a detecting circuit 6, and stored in an FF group 7. Accordingly, plural timers can be constituted of a proper updating circuit and only one overflow and underflow detecting circuit.</p>
申请公布号 JPS61255422(A) 申请公布日期 1986.11.13
申请号 JP19850097594 申请日期 1985.05.08
申请人 NEC CORP 发明人 IWATA ATSUSHI
分类号 G06F1/14;G06F1/04 主分类号 G06F1/14
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