| 摘要 |
PURPOSE:To obtain a bit clock which is synchronizing with the bit of an input signal supplied from an FF circuit by extracting the difference of phases between the output signal of the FF circuit which divides the output signal of a VCO circuit into two parts and the edge part of an input signal shown by a non- resetting method in the form of a change of pulse width. CONSTITUTION:When a pulse signal A is peoduced from a VCO 1, this signal A is supplied to a clock input terminal CK of the 1st FF circuit 2. The circuit 2 contains a 2-dividing circuit which divides the signal A into two parts. An output signal J of the 2nd exclusive OR gate 9 undergoes the modulation of pulse width in accordance with the difference of phases between the edge part of a reproduction signal E and a signal B. Then the signal J is smoothed by a loop filter 10 and supplied to the VCO 1 in the form of an oscillation frequency control signal to correct the oscillation frequency. Therefore the bit clock output produced from a reset output terminal -Q of the circuit 2 is synchronous with the signal E. In this case, a differentiating circuit using a resistance and a capacitor is not needed for a suitable application to integration. |
