| 摘要 |
PURPOSE:To reduce the hardware quantity of an interface and at the same time to discriminate the transfer order of data through a simple process by transferring data successively via an input/output register FIFO. CONSTITUTION:An independent access is possible at the input and output sides with a register FIFO4, and the FIFO4 delivers an input ready signal IR showing the presence or absence of an idle area in a memory region as well as an output ready signal OR showing the presence or absence of writing of data to the memory region. When it is needed to read the memory information of the FIFO4 while a microcomputer 6 for reception is using the data given from a microcomputer 1 for transmission, the computer 6 discriminates whether the signal OR is set at 1. Then a reading action is carried out if the signal OR is set at 1. Thus the frequent interruption processing can be omitted by transferring data via the FIFO4. This can reduce the hardware quantity and also discriminate the transfer order of data with a simple process. |
