| 摘要 |
PURPOSE:To prevent the formation of an inverted layer along an insulating and isolating layer and to decrease leading, by providing an inversion preventing P layer directly beneath an N<+> layer on the side of a P<-> well. CONSTITUTION:After an insulating and isolating film 6 and a P<-> will 7 are formed, a resist mask 17 is formed. B ions are implanted, and a P type inversion preventing layer 18, which has a peak at a depth of about 0.4mum in the well 7, is formed. When the resist is removed and isolated by an oxide film 9, the concentration distribution of the layer 18 is expanded. Then, an Si gate 11, an N<+> source and drain 12 and 13, an interlayer insulating film 14 and an electrode 15 are provided as specified, and an MOSIC is completed. In this constitution of the IC using the embedded insulating and isolating part, the formation of an inverted layer along the insulating and isolating film is prevented, especially owing to the presence of the P layer directly below the N<+> layer on the side of the insulating and isolating film of the N-channel FET on the side of the P<-> well. The yield of leaking is prevented. The part between the layers 12 and 13 is shortened and high degree of integration can be achieved. |
