发明名称 CPU SUPERVISORY CIRCUIT
摘要 PURPOSE:To self-return the temporary abnormal action due to a noise, etc., by outputting a signal to show the normal action from a CPU itself to the external part, making it to a prescribed time stop condition when a normal action signal is not outputted due to the abnormal occurrence and executing the restarting. CONSTITUTION:An output signal (e) of a latch circuit 4 is a high level and a CPU 1 is a normal action, and then, an output signal (d) of the second timer 3 is a high level, the first timer 2 is reset by an ordinary action signal (a) of the CPU 1 and started, and since the first timer period T2 is larger than the ordinary action signal (a) period T1, a pulse signal (c) is not outputted. After the first timer 2 is reset, when the tie T1 does not pass, abnormality is generated at the CPU 1, and then, after the time T2 passes from when the first timer 2 is finally reset, the pulse signal (c) is outputted, a latch circuit 4 comes to be a low level, the CPU 1 is reset and comes to be the stop condition, the second timer 3 is started, after the prescribed time passes, a pulse signal (d) is outputted and the CPU 1 is restarted.
申请公布号 JPS61255445(A) 申请公布日期 1986.11.13
申请号 JP19850097135 申请日期 1985.05.08
申请人 NEC CORP 发明人 INOUE AKIRA
分类号 G06F11/30;G06F11/00 主分类号 G06F11/30
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