| 摘要 |
PURPOSE:To shorten the wiring length of whole semiconductor chip, and to improve the efficiency of wirings by forming the internal wirings to each circuit block constituted by logic circuits consisting of a plurality of elements severally and the inter-block wirings communicated with desired blocks among the blocks while being mutually made parallel when a plurality of the circuit blocks are connected. CONSTITUTION:When a plurality of circuit blocks constituted by logic circuits consisting of a plurality of elements are arranged in the line direction or the row direction in an array division 51, block wiring regions 2 are disposed while holding inter-block wiring regions 1. In such constitution, second wiring layers 6 as internal wirings are each formed in several region 2, and inter-block wirings 4 for mutually connecting the desired regions 2 are each penetrated through the regions 1, and the wiring layers 6 and the wirings 4 are shaped only by desired numbers while being mutually made parallel. Accordingly, the efficiency of the inter-block wirings on the design of an IC is improved without bending the wirings 4. |
