| 摘要 |
PURPOSE:To improve the degree of integration of a CMOS device without damaging the dimensional accuracy of an element by dividing the thickness of a field insulating film into two kinds. CONSTITUTION:A P-channel FET with P<+> type source and drain is formed on an N type Si substrate 11, and an N-channel FET with N<+> type source and drain is formed on a P-well 12. The thickness c' of a field insulating film 15 is made differ from that d' of other field insulating films 16 at that time. Consequently, P-N isolation distance a'+b' can be made shorter than conventional devices because film thickness c' is thick. The threshold voltage of a parasitic MOS element increases with the enlargement of film thickness, and gradually increases with the augmentation of the isolation distance, and the titled device is saturated. As a result, the isolation distance may be small on large film thickness when threshold voltage is made constant, and the accuracy of a distance requires no accuracy as one in an element section. Accordingly, the isolation distance a'+b' can be made shorter than conventional devices, the thickness d' of the field insulating films 16 in other sections is formed in the same manner as conventional devices, and a CMOS device having the high degree of integration is obtained without damaging the dimensional accuracy by a bird beak in an LOCOS. |
