| 摘要 |
<p>A TTL flip-flop having improved AC and DC characteristics including a higher resistance to output degradation and quicker transition time from a high state to a low state. The flip-flop includes a master section (42) adapted to receive a data input signal (DIN) and a clock pulse (Cp) and includes a first output terminal (31') for providing a Q output signal and a second output terminal for providing a Q output signal. A slave section (45) is coupled between the master section and output buffers (46, 47) for latching the Q and Q outputs. The slave section comprises first and second latch portions, each responsive to a signal from the master section and coupled to one of the output buffers. The latch portions are similar and include a first transistor (56, 62) having a collector coupled to one output terminal and an emitter responsive to the data input signal. A second transistor (51, 52) has a first emitter coupled to the emitter of the first transistor and a third transistor (59, 64) has a collector coupled to the collector of the first transistor. A fourth transistor (57, 63) has a collector coupled to a second emitter of the second transistor and a base coupled to an emitter of the third transistor.</p> |
