| 摘要 |
PURPOSE:To detect the completion of equalization precisely by allowing a training signal received in prior to a data signal and passed through an automatic equalizer to detect continuously a symbol indicating a lag less than a set value from the training signal generated from the signal itself. CONSTITUTION:A training signal applied from an input terminal 1 is equalized through a controlled automatic equalizer A-EQL and then the equalized signal is applied from an output terminal 3 to an adder AD. The adder AD finds out the difference between a training signal generated from the adder AD itself and the equalized training signal, and applies the difference to a comparator COM. When the output signal from the adder AD is smaller than a set error value applied from an error setting part ES, the comparator COM generates an output and a counter COU counts up said output. When the number of taps of a delay line is about 40-60, (40-60)+alpha symbols smaller than the set error value are continuously measured to complete equalization. |
