| 摘要 |
PURPOSE:To avoid the data discordance, etc. due to the asynchronous processing by providing a transmisson timing control circuit at the transmission side to start transmission of data all at once and having collation of data at the reception side when the reception is through with a series of data. CONSTITUTION:A transmission timing control circuit set at the transmission side starts data transmission of own station at a time point when the transmission start signals of own station as well as other two stations which are sent via a timing detection line are all active. Then data transmitters start data transmission all at once. The signals sent from triplex processors are applied to frame processing circuits 404-406 via a data transmission circuit 400. Then data are extracted out of signal frames and stored successively to reception data buffers 410-412. The circuits 404-406 activate reception end signal 413-415 when detecting a close flag of the signal frame. When signals 413-415 are all active, the contents of buffers 410-412 are supplied to a multiplexed signal processing circuit 418 and then transferred to an input/output device after collation. |
