| 摘要 |
PURPOSE:To reduce the working load of a processor and at the same time to attain stable and assured input control to a memory, by using an output circuit which transmits successively data given from an input/output memory to the outside and an input control circuit. CONSTITUTION:For transfer of data, the parallel data given from a processor CPU are given successively to an input/output memory FIFO and stored once there. Then these parallel data are converted into serisl data via an output circuit OC and delivered in the form of the output data D0. In this case, an input control circuit ICT transmits a write start signal SI in accordance with the coincidence obtained between the conditions where a write command signal WT is given and those where a preparation end signal IR is given. As a result, matching is obtained between the signal WT and the state of the memory FIFO and therefore it is needed for the processor just to transmit a write command signal only. This circuit reduces the working load of the processor and also ensures the stable and assured input control to the memory. |
