| 摘要 |
PURPOSE:To improve the processing capacity of a concurrent method by producing all faults with a combined gate for simulation and inverting an input signal with a simple gate among plural logical circuits and to register a fault list connected to an input terminal whose output is inverted. CONSTITUTION:When the input vector of a simple gate is set at (1, 1), and evaluating part 6 inverts successively the bits of the input vector. If an output is inverted by the inversion of each bit of the input vector, ''1'' is set to the corresponding bit of a transmission mark register 10 with other bits kept at ''0''. A register part 9 registers the elements transmitted to fault lists (n) and (w) of a fault list memory 1 corresponding to the bit where ''1'' is set by the register 10. The corresponding is obtained among a fault list Ld, bit ''1'' of the input vector of an input/output register 5 and bit ''1'' of the register 10 respectively. In the same way, the correspondence is secured among a fault list Lc, bit ''2'' of the input vector of the register 5 and bit ''2'' of the register 10. |
