| 摘要 |
<p>PURPOSE:To avoid mulfunction by constituting a circuit that a detection signal of a frame synchronizing signal is outputted when the number of bits of one frame is counted and constituting the circuit that the shifted timing is to be corrected when the timing of the frame synchronizing signal is shifted with the pattern detection signal. CONSTITUTION:Suppose that the dissidence between the detecting signal S0 and a pulse S1 occurs consecutively, e.g., four times. That is, suppose that the 4th H level pulse output P is produced from an AND gate 10. Then a Qc output of a counter 12 goes to an H level in synchronizing with the rising of a clock CK'. Further, the nixt detecting signal S0 is generated at a period D and when an output S0' inverting signal S0 at an inverter 14 is applied to an NAND gate 8, an L level pulse is outputted from the NAND gate 8, pulse reset counters 3, 3, 3. That is, the state that the pulse S1 in synchronizing with the detection signal S0 of the frame synchronizing signal is generated is attained. Thus, the timing of both S0, S1 is made coincident at the next period E.</p> |
