发明名称 PULSE CIRCUIT
摘要 PURPOSE:To generate a pulse having excellent settling characteristics and accurate timing by inserting a resistor between a couple of output terminals outputting complementary pulses to each other to suppress the ringing at the differential mode. CONSTITUTION:The pulse circuit consists of an operating power supply 1, pulse sources 2A, 2B being in a complementary relation, transistors (TRs) 3A, 3B constituting a couple of emitter follower circuits, current sources 4A, 4B and logical circuits 8A, 8B constituting a load circuit, and the resistor 9 is inserted between the emitters of the TRs 3A, 3B. Although ringing occurs in the emitter output of the TRs 3A, 3B, since the mode of the ringing is in-phase, the ringings are cancelled by a differential output and a pulse without ringing is obtained. This is because the impedance of the differential mode is made lower than that of the common mode at the mutual output terminals by inserting the resistor 9.
申请公布号 JPS6041815(A) 申请公布日期 1985.03.05
申请号 JP19830150678 申请日期 1983.08.17
申请人 MATSUSHITA DENKI SANGYO KK 发明人 MATSUZAWA AKIRA;INOUE MICHIHIRO
分类号 H03K19/00;H03K5/00;H03K5/02;H03K17/60 主分类号 H03K19/00
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