发明名称 |
Transistor power amplifier circuit |
摘要 |
Two output transistors constituting a push-pull output amplifier circuit are connected in series between a power supply and a grounded point, and an output terminal is disposed at a point where the two output transistors are commonly connected. An operation detector circuit detects the operation of one output transistor. A level detector circuit detects a d-c voltage level at the output terminal. The two output transistors are driven by a drive circuit in a push-pull manner. The output of the operation detector circuit and the output of the level detector circuit control the drive circuit via a control circuit. When the operation detector circuit detected the fact that the operation of one output transistor has deviated beyond a predetermined detection level, the control circuit works to confine the operation of the abovementioned output transistor within a predetermined restriction level via the drive circuit. The power loss in the restriction level is smaller than the power loss in the detection level. During a period in which the output terminal is short-circuited to the grounded point in a d-c manner, the level detector circuit so controls the control circuit that the operation of the abovementioned one output transistor is confined within the restriction level.
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申请公布号 |
US4503478(A) |
申请公布日期 |
1985.03.05 |
申请号 |
US19790052207 |
申请日期 |
1979.06.26 |
申请人 |
HITACHI, LTD. |
发明人 |
SEKI, KUNIO;TAKESHITA, RITSUJI |
分类号 |
H03F1/42;H03F1/52;H03F3/20;H03F3/30;(IPC1-7):H02H7/20 |
主分类号 |
H03F1/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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