| 摘要 |
PURPOSE:To debug the contents of an ROM by using an external ROM in the debugging mode by switching a terminal of an LSI to the using state of a normal interface mode or that of an external ROM access mode. CONSTITUTION:In the debugging mode, a clock in the LSI is set up to 1/2 period, and each cycle length of an ROM address cycle, an ROM data reading cycle and an instruction execution cycle is made twice. An ROM address outputted to the LSI terminal at said timing is sent to the ROMB side by a selecting and distributing circuit S5. Data read out from the ROMB are supplied to the LSI by a distributing circuit S6 during the period of twice timing. In the LSI during an ROMB access mode period, an ROM address from a processor CC is returned to the terminal of the LSI by distribution circuits S1-S3 through the distribution circuit S2 and reading data are returned from the terminal of the LSI to the processor CC. |
