发明名称 TIMING SIGNAL EXTRACTING CIRCUIT
摘要 <p>PURPOSE:To eliminate the noise in opposite polarity mixed in an input signal by providing a digital interval detecting circuit waveform-shaping the input signal into one signal only when the time interval between the input signals is narrower than a preset prescribed time interval. CONSTITUTION:A timing TM signal inputted from a terminal 1 is inputted to the digital interval detecting circuit 28. The circuit 28 sets a time width being integer multiple of the time width of output signal of a fixed oscillator 3 as a prescribed time width, and only when the time interval of the inputted TM signal is narrower than the set time width, the input signals are waveform- shaped into one TM signal and inputted to a digital width detecting circuit 2. Thus, the division of the TM signal due to the mixture of the noise of opposite polarity having a prescribed time width or below is prevented. The time width being integer multiple of the output signal time width of an oscillator 3 is set to the circuit 2, and only when the time width of the input signal is wider than the set time width, the circuit 2 outputs a reset signal to a frequency divider circuit 4. Thus, in setting the time width so that the reset signal to the circuit 4 is outputted at the input of a true TM signal, the output signal of the circuit 4 and the true TM signal are synchronized.</p>
申请公布号 JPS6039947(A) 申请公布日期 1985.03.02
申请号 JP19830149025 申请日期 1983.08.15
申请人 SUWA SEIKOSHA KK 发明人 IKEJIRI HIROAKI
分类号 H04N5/08;H04L7/00;H04L7/027 主分类号 H04N5/08
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