| 摘要 |
PURPOSE:To speed-up the processing speed by providing a multiplexer, a binary counter and a tri-state gate or the like to a priority deciding circuit to relieve the load to software comprising software with fast processing speed. CONSTITUTION:An interruption priority deciding circuit is provided with N pieces of plural interruption cause storing FFs C1-Cn, and outputs of the FFs C1-Cn are inputted to a multiplexer E. The outputs of the FFs C1-Cn are inputted to an n-input NAND gate F, the output of which is fed to a 2-input AND gate G, and an enable signal is outputted to the binary counter H from the gate G and a counter H gives sequentially a signal to terminals Q1-Qn of the multiplexer E. The signal selects the outputs of the FFs C1-Cn, outputs an output signal (l) from the multiplexer E to inhibit the operation of the gate G. Further, the counter value of the counter H is fed to the tri-state gate I to output tri- state gate outputs i0-i7, thereby speeding up the processing speed. |
