| 摘要 |
PURPOSE:To reduce a chip area by providing respectively an inverter in addition to non-inverting input and output buffers in series and providing only one stage of an inverter to a latch circuit. CONSTITUTION:The IC is constituted by connecting n-stages of circuit blocks each comprising a shift register (SR)11, a latch circuit 12', a gate circuit 13, an output buffer BF1 and a transistor (TR) HV1. On the other hand, only one set of input buffer groups 22-27, input and output buffers 21, 21' and 28, 28' is provided to the IC chip. An input data at a DI terminal is inverted and the result is fetched to an input terminal of the SR11 in the IC of this constitution. The input buffers 21, 21' are constituted by a 3-stage of the inverters and the increase in the area is neglected in this case. A signal to an SRn is outputted in the same phase an the input signal from a terminal of an SOn by being waveform-shaped and inverted by non-inverting and inverting output buffers 28, 28'. In this case, the inverter 28' is increased by one stage to the output buffer section, but the area is neglected for the array form circuit. Since the number of inverters of the latch circuit 12' is decreased, the chip area is decreased. |
