| 摘要 |
PURPOSE:To improve the circuit integration of a semiconductor integrated circuit by using only one data transfer line and realizing the circuit with one transmission gate only. CONSTITUTION:The 2nd latch circuit 10 consists of two inverters Q3, Q4, an input side of the inverter Q3 is used as an input terminal of the 2nd latch circuit 10, an output of the inverter Q3 is connected to an input of the inverter Q4, an output of the inverter Q4 is connected to an input of the inverter Q3, and an output of the inverter Q3 is used as an output terminal of the 2nd latch circuit 10. The 1st transmission gate 11 consists of the 4N channel TRN4 and a data is transferred from the 1st latch circuit 1 to the 2nd latch circuit 10. Further, the 2nd transmission gate 12 consists of the 4N channel TRN4 so as to transfer a data from the 2nd latch circuit 10 to the 3rd latch circuit 3. Since the number of data transfer lines is decreased by using this CMOS latch circuit, the circuit integration of the semiconductor integrated circuit is increased. |
