| 摘要 |
As shown in (Fig. 2A), the fall time of an ECL gate (20) is precisely controlled using a fixed capacitor (46) which is connected between the positive supply voltage and the ECL gate output terminal (44), and a variable current source (48, 50, 52) connected between ground (GRND 3) and the ECL gate output terminal (44). A time-delay circuit is obtained by controlling the variable current source with an error voltage (VR2) of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates (12, 14, 16), as shown Fig. 1, with controlled fall times in a ring oscillator configuration. Addition of a noninverting input (19) to one ECL gate (16) makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided, as shown in Figs. 5A and 5B, by phase-locking the output signal of a first phase-locked loop (130) to a system reference signal (TCK) to generate a first-loop control voltage (X4). A second phase-locked loop is phase-locked to the received signal (MNCK) with a second-loop control voltage (VR4). In addition, the second phase-locked loop (142) is also frequency-locked to the system reference signal (TCK) by the first-loop control voltage (X4). This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal. |
