发明名称 GATE CIRCUIT
摘要 PURPOSE:To perform stably chip select, information write, etc. with a low power source voltage by providing two sets of differential amplifying circuit in parallel between a pair of power sources. CONSTITUTION:When a chip select signal CS' becomes low-level, a transistor TRQ44 out of TRs Q43 and Q44 of the voltage comparing differential amplifying circuit connected between a pair of power sources is turned off, and a current is flowed to a resistance 36, and a voltage drops. Then, TRs Q54 and Q53 are turned off, and the output of an OR circuit 21 is inverted to the low level by TRs Q51 and Q52 held in the turn-off and on state, and the output of an OR circuit 22 is held in the high level, and chip select is executed. Similarly, write is controlled through TRs Q41 and Q42 which are connected in parallel between a pair of power sources and constitute the differential amplifying circuit. By this parallel connection, it is unnecessary to make the power source voltage high- level in distinction from a constitution where plural voltage comparing circuit are connected vertically to set different reference voltages, and chip select, information write, etc. are performed stably with a low power source voltage.
申请公布号 JPS6038791(A) 申请公布日期 1985.02.28
申请号 JP19830146350 申请日期 1983.08.12
申请人 HITACHI SEISAKUSHO KK 发明人 AOKI HIDEYUKI;MITSUMOTO KINYA
分类号 G11C11/414;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/414
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