| 摘要 |
PURPOSE:To prevent a latch-up positively without the increase of the area of a layout by interposing an isolation region between each forming region of MOS field-effect transistors of two kinds constituting a C-MOS logical circuit. CONSTITUTION:p<+> type isolation layers 16 to which a p type conductive impurity is diffused selectively in high concentration are formed to an epitaxial layer 12 so as to reach to a substrate 10. An isolation region electrically isolating each forming region Ap, An in a pair of MOS field-effect transistors Qp, Qn constituting a C-MOS logical circuit mutually is formed by the isolation layer 16. Accordingly, the formation of a positive feedback loop for generating a latch-up is obstructed by shaping an electrical barrier partially interrupting a section between the two regions Ap, An, thus obtaining a sufficient latch-up preventive effect. |
