发明名称 REFRESH CONTROL CIRCUIT
摘要 PURPOSE:To reduce the number of input/output pins to facilitate making a circuit into an LSI by converting a refresh address to serial data and reconverting it to parallel data. CONSTITUTION:Up-counting of a refresh address counter 3 is started through a refresh address control circuit 2 in accordance with an interrupt signal from a request acceptance control circuit 103. A parallel refresh address outputted from the counter 3 is converted to serial data by a refresh address bit selecting circuit 105 and is supplied to a shift register 102 through one pin and is reconverted to parallel data and is stored in a refresh address register 104. By this transfer of serial data, the number of output/input pins is reduced and the refresh circuit including the register 102 and following circuits can be taken easily in the refresh control circuit which is made into an LSI and includes circuits up to the refresh address bit selecting circuit.
申请公布号 JPS6038795(A) 申请公布日期 1985.02.28
申请号 JP19830146869 申请日期 1983.08.11
申请人 NIPPON DENKI KK 发明人 OONO KUNIO
分类号 G11C11/406;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/406
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