发明名称 MEMORY SYSTEM
摘要 PURPOSE:To realize a parallel processing and to improve the processing efficiency for a write instruction with inspection by separating the reading and writing circuits corresponding to a memory from an instruction execution control circuit and performing a read inspection based on the write instruction with inspection. CONSTITUTION:A memory 41 is selected by the instruction execution circuit 1 and the write instruction with inspection is executed by an instruction given from a channel device. Then the writing is carried out to the memory 41 via a reading/writing circuit 2 set oppositely to the memory 41. The presence or absence of an error is detected through the reading of the memory 41 by an error detection code generating/inspecting circuit 22, and the like of the circuit 2. Then the result of this detection is reported to the circuit 1. This error inspection is carried out by the circuit 2 separated from the circuit 1. Meanwhile another reading/writing circuit 3, and the like are controlled by the circuit 1, and the parallel writing processing is possible to another memory 51, and the like to improve the processing efficiency for the write instruction with inspection.
申请公布号 JPS6038766(A) 申请公布日期 1985.02.28
申请号 JP19830145034 申请日期 1983.08.10
申请人 NIPPON DENKI KK 发明人 HASHIMOTO HISAO
分类号 G11B20/18;(IPC1-7):G11B20/18 主分类号 G11B20/18
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