| 摘要 |
<p>A digital data bus system operating asychronously with a fixed clock and having a automatically variable data rate selected by sending and receiving units. A master clock is generated by a master controller and distributed to one or more peripheral controllers of the data bus system through a single clock line. In addition to address/data lines, a single handshake hold signal is shared by the master and all peripheral controllers. All data transfers are executed on a bus clock pulse and data transfer rate is controlled by the sending and receiving units through operation of the hold signal. A receiving unit not ready to receive information on the bus will assert hold signal on hold signal line and the transmitting unit will maintain the information presently on the bus during each clock period in of which hold signal is asserted. Data transfer is executed on next clock pulse after termination of hold signal. All information transfers are thereby synchronous with the single frequency bus clock, but data transfer rate is variable and automatically determined by the sending and receiving units.</p> |
