| 摘要 |
PURPOSE:To obtain a pipeline controlling system which is optimum to a microcomputer by constituting said system so that all the function units start simultaneously the next basic processing in accordance with the execution procedure, and the execution of the prescribed next instruction is started. CONSTITUTION:A stage start signal 7-7' is AND of each output of the first, the second and the third stage end FFs 7-4, 7-5 and 7-6 obtained by an AND gate 7-7. When the stage start signal 7-7' is inputted, each function unit of a bus interface part 7-1, an operand address calculating part 7-2 and an executing part 7-3 resets the first, the second and the third stage end FFs 7-4, 7-5 and 7-6, and simultaneously starts processing of the next one stage portion. A timing storage part 7-8 holds a timing signal which is set in advance so that the next signal can be started without collision, and sends out its timing signal at prescrived timing. |
