| 摘要 |
<p>PURPOSE:To reduce the number of connecting terminals to a memory part of a central processing part without decreasing a data processing speed by switching as to whether a transfer destination is program storage or data storage, in accordance with the kind of an executing instruction. CONSTITUTION:In case when it is shown to be processing data access by a DATA signal, the first AND gate groups A1-An are opened, the second AND gate groups B1-Bn are closed, and address information DA1-DAn of a data memory part is outputted to terminals P1-Pn. Also, in case when it is shown that no processing data access exists by the DATA signal, an output of an inverting circuit I to which its signal is inputted becomes effective, the first AND gate groups A1-An are closed, the second AND gate groups B1-Bn are opened, and address information PA1-PAn of a program memory part is outputted to the terminals P1-Pn. This output is connected to an address information transfer line 31 to both the program and data memory parts 2, 3 from a central processing part 1.</p> |
