发明名称 SYSTEM FOR TESTING AND INDICATING THE OPERATING CONDITION OF A LOGIC CIRCUIT
摘要 1. System for testing and displaying the operating condition of a logic circuit (CL), comprising simulation means (MS) having command outputs, for applying operation-simulating logic signals to inputs of the logic circuit (CL), sampling means (MP) for sampling at the outputs of the logic circuit (CL) the logic state of signals resulting from the application of operation-simulating logic signals to the inputs of the logic circuit (CL) and for sampling the logic state of those signals applied to the inputs of the logic circuit (CL), characterized in that it additionally comprises a display means (MV) having a screen (E), a mask (C) adapted to cover at least a part of the screen (E), said mask occupying a predetermined position with respect to the screen and having lines (L) representing links between certain predetermined components of said logic circuit (CL) and windows (F) representing said predetermined components, and command means (MC) connected to the display means (MV) and the sampling means (MP), the command means (MC) being adapted to command the display means (MV) whereby it displays, for each of said predetermined components and in the windows (F) corresponding respectively to each of said predetermined components, information relating at least to the operating condition of the respective component, to its location in the circuit and to the possible transmission to the output of a signal received at the input of said component.
申请公布号 DE3261786(D1) 申请公布日期 1985.02.21
申请号 DE19823261786 申请日期 1982.01.22
申请人 COMMISSARIAT A L'ENERGIE ATOMIQUE ETABLISSEMENT DE CARACTERE SCIENTIFIQUE TECHNIQUE ET INDUSTRIEL 发明人 LAVIRON, ANDRE;BERARD, CLAUDE
分类号 G01R31/28;G06F11/26;G06F17/50;H03K19/00;(IPC1-7):G01R31/28 主分类号 G01R31/28
代理机构 代理人
主权项
地址