| 摘要 |
<p>PURPOSE:To enlarge the processing capacity of a control apparatus with low cost by providing a latch means for data pass between a microcomputer and a peripheral control circuit to compensate for the deviation of data supply and reception timing due to difference between clock frequencies. CONSTITUTION:An engine control apparatus 1 is provided with a microcomputer 2 and a peripheral control circuit 3. Data from the high speed microcomputer 2, as they are, are supplied to the data inputs D0-D7 of LSI3 through respective buffers 83 of interface circuits 8A-8H and written in a register in this LSI3. Data from the low speed LSI3 are once written in respective latch circuits 81 in the interface circuits 8A-8H with a predetermined timing and the outputs of said circuits are combined with I/O ports P10-P17 of the microcomputer 2. Thus, an interface between the high speed microcomputer and the low speed peripheral control circuit can be always ensured.</p> |
